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HD6432351 Datasheet, PDF (833/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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TIER5âTimer Interrupt Enable Register 5
H'FEA4
TPU5
Bit
:
Initial value :
Read/Write :
7
TTGE
0
R/W
6
5
4
3
â TCIEU TCIEV â
1
0
0
0
â
R/W R/W
â
2
1
0
â TGIEB TGIEA
0
0
0
â
R/W R/W
TGR Interrupt Enable A
0 Interrupt requests (TGIA)
by TGFA bit disabled
1 Interrupt requests (TGIA)
by TGFA bit enabled
TGR Interrupt Enable B
0 Interrupt requests (TGIB)
by TGFB bit disabled
1 Interrupt requests (TGIB)
by TGFB bit enabled
Overflow Interrupt Enable
0 Interrupt requests (TCIV) by TCFV disabled
1 Interrupt requests (TCIV) by TCFV enabled
Underflow Interrupt Enable
0 Interrupt requests (TCIU) by TCFU disabled
1 Interrupt requests (TCIU) by TCFU enabled
A/D Conversion Start Request Enable
0 A/D conversion start request generation disabled
1 A/D conversion start request generation enabled
813
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