HD6432351 Datasheet, PDF (437/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 7 Bit 6 Bit 5 Bit 4
Channel IOB3 IOB2 IOB1 IOB0 Description
3
0 0 0 0 TGR3B is Output disabled
(Initial value)
1
output _{Initial output is 0 0 output at compare match}
1
0
compare _output
register
1 output at compare match
1
Toggle output at compare
match
100
Output disabled
1
10
Initial output is 1 0 output at compare match
output
1 output at compare match
1
Toggle output at compare
match
1 0 0 0 TGR3B is Capture input Input capture at rising edge
1
input
source is
capture TIOCB3 pin
1
*
register
Input capture at falling edge
Input capture at both edges
1
*
*
Capture input Input capture at TCNT4
source is channel count-up/count-down*¹
4/count clock
*: Don’t care
Note: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the TCNT4
count clock, this setting is invalid and input capture is not generated.
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