HD6432351 Datasheet, PDF (856/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DMACR0A—DMA Control Register 0A
DMACR0B—DMA Control Register 0B
DMACR1A—DMA Control Register 1A
DMACR1B—DMA Control Register 1B
H'FF02
H'FF03
H'FF04
H'FF05
DMAC
DMAC
DMAC
DMAC
Full address mode
Bit
: 15
14
13
12
11
10
9
8
DMACRA : DTSZ SAID SAIDE BLKDIR BLKE
—
—
—
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W R/W
R/W R/W R/W
R/W R/W
Block Direction/Block Enable
0 0 Transfer in normal mode
1 Transfer in block transfer mode, destination side is block area
1 0 Transfer in normal mode
1 Transfer in block transfer mode, source side is block area
Source Address Increment/Decrement
0 0 MARA is fixed
1 MARA is incremented after a data transfer
1 0 MARA is fixed
1 MARA is decremented after a data transfer
Data Transfer Size
0 Byte-size transfer
1 Word-size transfer
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