HD6432351 Datasheet, PDF (525/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

11.3.2 Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 11-3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
ø
TCNT
TGRA
Compare match
A signal
NDRH
PODRH
PO8 to PO15
N
N+1
N
n
m
m
n
n
Figure 11-3 Timing of Transfer and Output of NDR Contents (Example)
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