HD6432351 Datasheet, PDF (57/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

2.5.2 Memory Data Formats
Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data
in memory, but word or longword data must begin at an even address. If an attempt is made to
access word or longword data at an odd address, no address error occurs but the least significant
bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to
instruction fetches.
Data Type
1-bit data
Address
Data Format
7
0
Address L 7 6 5 4 3 2 1 0
Byte data
Address L MSB
LSB
Word data
Address 2M MSB
Address 2M + 1
LSB
Longword data
Address 2N MSB
Address 2N + 1
Address 2N + 2
Address 2N + 3
LSB
Figure 2-11 Memory Data Formats
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
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