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HD6432351 Datasheet, PDF (65/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Table 2-3 Instructions Classified by Function (cont)
Type
Logic
operations
Instruction
AND
Size*
B/W/L
OR
B/W/L
XOR
B/W/L
NOT
B/W/L
Shift
operations
SHAL
SHAR
B/W/L
SHLL
SHLR
B/W/L
ROTL
ROTR
B/W/L
ROTXL
ROTXR
B/W/L
Note: * Size refers to the operand size.
B: Byte
W: Word
L: Longword
Function
Rd ⧠Rs â Rd, Rd ⧠#IMM â Rd
Performs a logical AND operation on a general register
and another general register or immediate data.
Rd ⨠Rs â Rd, Rd ⨠#IMM â Rd
Performs a logical OR operation on a general register
and another general register or immediate data.
Rd â Rs â Rd, Rd â #IMM â Rd
Performs a logical exclusive OR operation on a general
register and another general register or immediate data.
¬ (Rd) â (Rd)
Takes the one's complement of general register
contents.
Rd (shift) â Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
Rd (shift) â Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
Rd (rotate) â Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
Rd (rotate) â Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
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