HD6432351 Datasheet, PDF (848/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

RTCNT—Refresh Timer Counter
Bit
:
7
6
5
H'FED8
4
3
2
Bus Controller
1
0
Initial value :
0
0
0
0
0
0
0
0
Read/Write :
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Internal clock count value
RTCOR—Refresh Time Constant Register
H'FED9
Bit
:
7
6
5
4
3
2
Bus Controller
1
0
Initial value :
Read/Write :
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Sets the period for compare match operations with RTCNT
MAR0AH—Memory Address Register 0AH
MAR0AL—Memory Address Register 0AL
H'FEE0
H'FEE2
DMAC
DMAC
Bit
:
MAR0AH :
Initial value :
Read/Write :
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————
00000000* * * ** * **
— — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR0AL :
Initial value : * * * * * * * * * * * * * * * *
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* : Undefined
In short address mode: Specifies transfer source/transfer destination address
In full address mode: Specifies transfer source address
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