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| HD6432351 Datasheet, PDF (843/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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WCRLâWait Control Register L
H'FED3
Bus Controller
Bit
:
Initial value :
Read/Write :
7
W31
1
R/W
6
W30
1
R/W
5
W21
1
R/W
4
W20
1
R/W
3
W11
1
R/W
2
W10
1
R/W
1
W01
1
R/W
0
W00
1
R/W
Area 0 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 1 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 2 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
Area 3 Wait Control
0 0 Program wait not inserted
1 1 program wait state inserted
1 0 2 program wait states inserted
1 3 program wait states inserted
823
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