HD6432351 Datasheet, PDF (578/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 13-8 SMR Settings and Serial Transfer Format Selection
Bit 7
C/A
0
1
SMR Settings
Bit 6
CHR
0
Bit 2
MP
0
Bit 5
PE
0
1
1
0
1
0
1
—
—
1
—
—
—
—
—
Bit 3
STOP Mode
Data
Length
0
Asynchronous
8-bit data
1
mode
0
1
0
7-bit data
1
0
1
0
Asynchronous
8-bit data
1
mode (multi-
processor
0
format)
1
7-bit data
—
Clocked
8-bit data
synchronous mode
SCI Transfer Format
Multi
Processor
Bit
Parity
Bit
Stop Bit
Length
No
No
1 bit
2 bits
Yes
1 bit
2 bits
No
1 bit
2 bits
Yes
1 bit
2 bits
Yes
No
1 bit
2 bits
1 bit
2 bits
No
None
Table 13-9 SMR and SCR Settings and SCI Clock Source Selection
SMR
Bit 7
C/A
0
1
SCR Setting
Bit 1 Bit 0
CKE1 CKE0 Mode
0
0
Asynchronous
1
mode
Clock
Source
Internal
1
0
External
1
0
0
Clocked
Internal
1
synchronous
mode
1
0
External
1
SCI Transmit/Receive Clock
SCK Pin Function
SCI does not use SCK pin
Outputs clock with same frequency as bit
rate
Inputs clock with frequency of 16 times
the bit rate
Outputs serial clock
Inputs serial clock
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