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HD6432351 Datasheet, PDF (307/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Bits 3 and 2âDTC Mode (MD1, MD0): These bits specify the DTC transfer mode.
Bit 3
MD1
0
1
Bit 2
MD0
0
1
0
1
Description
Normal mode
Repeat mode
Block transfer mode
â
Bit 1âDTC Transfer Mode Select (DTS): Specifies whether the source side or the destination
side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Bit 1
DTS
0
1
Description
Destination side is repeat area or block area
Source side is repeat area or block area
Bit 0âDTC Data Transfer Size (Sz): Specifies the size of data to be transferred.
Bit 0
Sz
0
1
Description
Byte-size transfer
Word-size transfer
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