HD6432351 Datasheet, PDF (146/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2.3 Wait Control Registers H and L (WCRH, WCRL)
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of
program wait states for the external space . The settings of bits W71, W70 to W11, and W10 have
no effect on operation.
Program waits are not inserted in the case of on-chip memory or internal I/O registers.
WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode.
They are not initialized by a manual reset or in software standby mode.
(1) WCRH
Bit
:
Initial value :
R/W
:
7
W71
1
R/W
6
W70
1
R/W
5
W61
1
R/W
4
W60
1
R/W
3
W51
1
R/W
2
W50
1
R/W
1
W41
1
R/W
0
W40
1
R/W
Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of
program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set
to 1.
Bit 7
W71
0
1
Bit 6
W70
0
1
0
1
Description
Program wait not inserted when external space area 7 is accessed
1 program wait state inserted when external space area 7 is accessed
2 program wait states inserted when external space area 7 is accessed
3 program wait states inserted when external space area 7 is accessed
(Initial value)
126