HD6432351 Datasheet, PDF (631/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Start
Initialization
Start transmission
No
ERS=0?
Yes
No
TEND=1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
No
All data transmitted?
Yes
No
ERS=0?
Yes
No
TEND=1?
Yes
Clear TE bit to 0
Error processing
End
Figure 14-4 Example of Transmission Processing Flow
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