HD6432351 Datasheet, PDF (203/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

EXTAL
Address
RD
HWR
RAS
CAS, LCAS
Data bus
DRAM space read
T_p T_r
T_c1 T_c2
External read
DRAM space write
T₁
T₁
T₂
T₃ T_c1 T_c1 T_c2
Idle cycle
Figure 6-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1)
6.8.2 Pin States in Idle Cycle
Table 6-8 shows pin states in an idle cycle.
Table 6-8 Pin States in Idle Cycle
Pins
Pin State
A₂₃ to A₀
D₁₅ to D₀
CSn
Contents of next bus cycle
High impedance
High*
CAS
High
AS
High
RD
High
HWR
High
LWR
High
DACKn
High
Note: * Remains low in DRAM space RAS down mode or a refresh cycle.
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