HD6432351 Datasheet, PDF (874/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PODRH — Output Data Register H
PODRL — Output Data Register L
PODRH
H'FF4A
H'FF4B
PPG
PPG
Bit
:
Initial value :
Read/Write :
7
POD15
0
R/(W)*
6
POD14
0
R/(W)*
5
POD13
0
R/(W)*
4
POD12
0
R/(W)*
3
POD11
0
R/(W)*
2
POD10
0
R/(W)*
1
POD9
0
R/(W)*
0
POD8
0
R/(W)*
PODRL
Stores output data for use in pulse output
Bit
:
Initial value :
Read/Write :
7
POD7
0
R/(W)*
6
POD6
0
R/(W)*
5
POD5
0
R/(W)*
4
POD4
0
R/(W)*
3
POD3
0
R/(W)*
2
POD2
0
R/(W)*
1
POD1
0
R/(W)*
0
POD0
0
R/(W)*
Stores output data for use in pulse output
Note: * A bit that has been set for pulse output by NDER is read-only.
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