HD6432351 Datasheet, PDF (807/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Address Register
(low) Name Bit 7
H’FEC4 IPRA —
Bit 6
IPR6
Bit 5
IPR5
Bit 4
IPR4
Bit 3
—
Bit 2
IPR2
Bit 1
IPR1
Bit 0
IPR0
H’FEC5 IPRB —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FEC6 IPRC —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FEC7 IPRD —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FEC8 IPRE —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FEC9 IPRF —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FECA IPRG —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FECB IPRH —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FECC IPRI
—
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FECD IPRJ —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FECE IPRK —
IPR6 IPR5 IPR4 —
IPR2 IPR1 IPR0
H’FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0
H’FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
H’FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40
H’FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00
H’FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMST0
H’FED5 BCRL BRLE BREQOE EAE —
LCASS —
WDBE WAITE
H’FED6 MCR TPC BE
RCDM CW2 MXC1 MXC0 RLW1 RLW0
H’FED7 DRAMCR RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0
H’FED8 RTCNT
H’FED9 RTCOR
H’FEE0 MAR0AH —
—
—
—
—
—
—
—
H’FEE1
H’FEE2 MAR0AL
H’FEE3
H’FEE4 IOAR0A
H’FEE5
H’FEE6 ETCR0A
H’FEE7
H’FEE8 MAR0BH —
—
—
—
—
—
—
—
H’FEE9
H’FEEA MAR0BL
H’FEEB
H’FEEC IOAR0B
H’FEED
H’FEEE ETCR0B
H’FEEF
Module Name
Interrupt
controller
Data Bus
Width
8 bit
Bus controller 8 bit
DMAC
16 bit
787