HD6432351 Datasheet, PDF (720/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

21.3.4 DMAC Timing
Table 21-7 lists the DMAC timing.
Table 21-7 DMAC Timing
Condition A: V_CC = 2.7 V to 5.5 V, AV_CC = 2.7 V to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
DREQ setup time
DREQ hold time
TEND delay time
DACK delay time 1
DACK delay time 2
Condition A Condition B
Symbol Min Max Min Max Unit
t _DRQS
40 — 30 — ns
t _DRQH
10 — 10 —
t _TED
— 40 — 20
t _DACD1
—
40
—
20
ns
t _DACD2
—
40
—
20
Test Conditions
Figure 21-21
Figure 21-20
Figure 21-18,
Figure 21-19
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