HD6432351 Datasheet, PDF (845/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

BCRL—Bus Control Register L
H'FED5
Bus Controller
Bit
:
Initial value :
Read/Write :
7
6
5
BRLE BREQOE —
0
0
1
R/W
R/W R/W
4
LCASS
1
R/W
3
DDS
1
R/W
2
1
0
— WDBE WAITE
1
0
0
R/W
R/W
R/W
WAIT Pin Enable
0 Wait input by WAIT
pin disabled
1 _{Wait input by WAIT}
pin enabled
Write Data Buffer Enable
0 _{Write data buffer}
function not used
1 _{Write data buffer}
function used
Reserved
Only 1 should be written to this bit
DACK Timing Select
When DMAC single address transfer is performed in
0 DRAM/PSRAM space, full access is always executed
DACK signal goes low from Tr or T1 cycle
Burst access is possible when DMAC single address
1 transfer is performed in DRAM/PSRAM space
DACK signal goes low from Tc1 or T2 cycle
LCAS Select
Write 0 to this bit when using the DRAM interface
Reserved
Only 0 should be written to this bit
BREQO Pin Enable
0 BREQO output disabled
1 BREQO output enabled
Bus Release Enable
0 External bus release is disabled
1 External bus release is enabled
825