HD6432351 Datasheet, PDF (397/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Port D Data Register (PDDR) [H8S/2351 Only]
Bit
:
Initial value :
R/W
:
7
PD7DR
0
R/W
6
PD6DR
0
R/W
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD₇ to
PD₀).
PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port D Register (PORTD) [H8S/2351 Only]
Bit
:
7
6
5
4
PD7
PD6 PD5
PD4
Initial value :
—*
—*
—*
—*
R/W
:
R
R
R
R
Note: * Determined by state of pins PD7 to PD0.
3
PD3
—*
R
2
PD2
—*
R
1
PD1
—*
R
0
PD0
—*
R
PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port D pins (PD₇ to PD₀) must always be performed on PDDR.
If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D
read is performed while PDDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin
states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset,
and in software standby mode.
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