HD6432351 Datasheet, PDF (781/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-5 Number of Cycles in Instruction Execution (cont)
Instruction
MAC
MOV
Mnemonic
MAC @ERn+,@ERm+
MOV.B #xx:8,Rd
MOV.B Rs,Rd
MOV.B @ERs,Rd
MOV.B @(d:16,ERs),Rd
MOV.B @(d:32,ERs),Rd
MOV.B @ERs+,Rd
MOV.B @aa:8,Rd
MOV.B @aa:16,Rd
MOV.B @aa:32,Rd
MOV.B Rs,@ERd
MOV.B Rs,@(d:16,ERd)
MOV.B Rs,@(d:32,ERd)
MOV.B Rs,@-ERd
MOV.B Rs,@aa:8
MOV.B Rs,@aa:16
MOV.B Rs,@aa:32
MOV.W #xx:16,Rd
MOV.W Rs,Rd
MOV.W @ERs,Rd
MOV.W @(d:16,ERs),Rd
MOV.W @(d:32,ERs),Rd
MOV.W @ERs+,Rd
MOV.W @aa:16,Rd
MOV.W @aa:32,Rd
MOV.W Rs,@ERd
MOV.W Rs,@(d:16,ERd)
MOV.W Rs,@(d:32,ERd)
MOV.W Rs,@-ERd
MOV.W Rs,@aa:16
MOV.W Rs,@aa:32
MOV.L #xx:32,ERd
MOV.L ERs,ERd
MOV.L @ERs,ERd
MOV.L @(d:16,ERs),ERd
MOV.L @(d:32,ERs),ERd
MOV.L @ERs+,ERd
MOV.L @aa:16,ERd
MOV.L @aa:32,ERd
MOV.L ERs,@ERd
MOV.L ERs,@(d:16,ERd)
Branch
Instruction Address
Fetch
Read
Stack Byte Data Word Data Internal
Operation Access Access Operation
I
J
K
L
M
N
Cannot be used in the H8S/2350 Series
1
1
1
1
2
1
4
1
1
1
1
1
1
2
1
3
1
1
1
2
1
4
1
1
1
1
1
1
2
1
3
1
2
1
1
1
2
1
4
1
1
1
1
2
1
3
1
1
1
2
1
4
1
1
1
1
2
1
3
1
3
1
2
2
3
2
5
2
2
2
1
3
2
4
2
2
2
3
2
761