HD6432351 Datasheet, PDF (156/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bits 3 and 2—Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the
shift to the lower half of the row address in row address/column address multiplexing for the
DRAM interface. In burst operation on the DRAM interface, these bits also select the row address
to be used for comparison.
Bit 3
MXC1
0
1
Bit 2
MXC0
0
1
0
1
Description
8-bit shift
(Initial value)
• When 8-bit access space is designated: Row address A₂₃ to A₈ used
for comparison
• When 16-bit access space is designated: Row address A₂₃ to A₉ used
for comparison
9-bit shift
• When 8-bit access space is designated: Row address A₂₃ to A₉ used
for comparison
• When 16-bit access space is designated: Row address A₂₃ to A₁₀ used
for comparison
10-bit shift
• When 8-bit access space is designated: Row address A₂₃ to A₁₀ used
for comparison
• When 16-bit access space is designated: Row address A₂₃ to A₁₁ used
for comparison
—
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
Bit 1
RLW1
0
1
Bit 0
RLW0
0
1
0
1
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
(Initial value)
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