HD6432351 Datasheet, PDF (887/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

P3ODR—Port 3 Open Drain Control Register H'FF76
Port 3
Bit
:
7
6
5
4
3
2
1
0
—
— P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
Initial value : _{Undefined Undefined 0}
0
0
0
0
0
Read/Write : _—
—
R/W
R/W
R/W
R/W
R/W
R/W
Controls the PMOS on/off status for each port 3 pin (P3₅ to P3₀)
PAODR—Port A Open Drain Control Register H'FF77
Port A
[H8S/2351 Only]
Bit
:
7
6
5
4
3
2
1
0
PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W R/W
R/W R/W R/W
R/W R/W
Controls the PMOS on/off status for each port A pin (PA₇ to PA₀)
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