HD6432351 Datasheet, PDF(58/989 Page) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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HD6432351 Datasheet, PDF (58/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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2.6 Instruction Set

2.6.1 Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2-1.

Table 2-1 Instruction Classification

Function

Instructions

Size Types

Data transfer

MOV

BWL 5

POP*1, PUSH*1

WL

LDM, STM

L

MOVFPE, MOVTPE*3

B

Arithmetic

operations

ADD, SUB, CMP, NEG

ADDX, SUBX, DAA, DAS

BWL 19

B

INC, DEC

BWL

ADDS, SUBS

L

MULXU, DIVXU, MULXS, DIVXS

BW

EXTU, EXTS

WL

TAS

B

Logic operations AND, OR, XOR, NOT

BWL 4

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL 8

Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, B

14

BIAND, BOR, BIOR, BXOR, BIXOR

Branch

Bcc*2, JMP, BSR, JSR, RTS

â

5

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP â

9

Block data transfer EEPMOV

â

1

Notes: B-byte size; W-word size; L-longword size.

1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-

SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,

@-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in the H8S/2350 Series.

38

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