HD6432351 Datasheet, PDF (201/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

(3) Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6-33.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
ø
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
ø
Address bus
CS (area A)
CS (area B)
RD
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Possibility of overlap between
CS (area B) and RD
(a) Idle cycle not inserted
(ICIS1 = 0)
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6-33 Relationship between Chip Select (CS) and Read (RD)
(4) Usage Notes
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of
consecutive reads between different areas, for example, if the second access is a DRAM access,
only a T_p cycle is inserted, and a T_I cycle is not. The timing in this case is shown in figure 6-34.
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6-35 (a) and (b).
181