HD6432351 Datasheet, PDF (406/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.13.2 Register Configuration
Table 9-23 shows the port F register configuration.
Table 9-23 Port F Registers
Name
Abbreviation
R/W
Port F data direction register
PFDDR
W
Port F data register
PFDR
R/W
Port F register
PORTF
R
Notes: 1. Lower 16 bits of the address.
2. Initial value depends on the mode.
Initial Value
H'80/H'00*²
H'00
Undefined
Address *¹
H'FEBE
H'FF6E
H'FF5E
Port F Data Direction Register (PFDDR)
Bit
:
7
6
5
4
3
2
1
0
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR
Modes 1, 2, 4, 5, 6
Initial value :
1
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
Modes 3 and 7
Initial value :
0
0
0
0
0
0
0
0
R/W
:
W
W
W
W
W
W
W
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,
4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
• Modes 1, 4, and 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351]
Pin PF₇ functions as the ø output pin when the corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF₆ to PF₃, which are
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
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