HD6432351 Datasheet, PDF (495/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting
of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing.
ø
Input capture
signal
TCNT
N
TGR
N
TGF flag
TGI interrupt
Figure 10-43 TGI Interrupt Timing (Input Capture)
475