HD6432351 Datasheet, PDF (972/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Mode 1/2*/3*/7*
PG_n
Mode 4/5/6*
Reset
R
Q
D
PGnDDR
C
WDDRG
Reset
R
Q
D
PGnDR
C
WDRG
RDRG
Bus controller
Chip select
RPORG
Legend
WDDRG : Write to PGDDR
WDRG : Write to PGDR
RDRG : Read PGDR
RPORG : Read port G
n = 1, 2, 3
Note: Modes 2, 3, 6, and 7 only apply to the H8S/2351.
Figure C-13 (b) Port G Block Diagram (Pins PG₁ to PG₃)
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