HD6432351 Datasheet, PDF (635/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

When the TEND flag in SSR is set to 1, a TXI interrupt request is generated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.
When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated.
The relationship between the operating states and interrupt sources is shown in table 14-8.
Table 14-8 Smart Card Mode Operating States and Interrupt Sources
Operating State
Transmit Normal
Mode
operation
Error
Receive Normal
Mode
operation
Error
Flag
TEND
Enable Bit
TIE
Interrupt DMAC
Source Activation
TXI
Possible
DTC
Activation
Possible
ERS
RIE
RDRF
RIE
ERI
Not possible Not possible
RXI
Possible
Possible
PER, ORER RIE
ERI
Not possible Not possible
Data Transfer Operation by DMAC or DTC: In smart card mode, as with the normal SCI,
transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is
also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the
TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC
will be activated by the TXI request, and transfer of the transmit data will be carried out. The
TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the
DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The
TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the
number of bytes specified by the SCI and DMAC are transmitted automatically even in
retransmission following an error. However, the ERS flag is not cleared automatically when an
error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be
generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or
DTC before carrying out SCI setting. For details of the DMAC and DTC setting procedures, see
section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC).
In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC
or DTC will be activated by the RXI request, and transfer of the receive data will be carried out.
The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or
DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or
DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error
flag should be cleared.
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