HD6432351 Datasheet, PDF (413/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• Modes 3 and 7 [H8S/2351 only]
Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing
the bit to 0 makes the pin an input port.
• Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351]
Pins PG₄ to PG₁ function as bus control output pins (CS0 to CS3) when the corresponding
PGDDR bits are set to 1, and as input ports when the bits are cleared to 0.
Pin PG₀ functions as the CAS output pin when DRAM interface is designated. Otherwise,
setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit
to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus
Controller.
Port G Data Register (PGDR)
Bit
:
7
6
5
4
3
2
1
0
—
—
— PG4DR PG3DR PG2DR PG1DR PG0DR
Initial value : Undefined Undefined Undefined 0
0
0
0
0
R/W
:
—
—
—
R/W
R/W
R/W
R/W
R/W
PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG₄ to
PG₀).
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It
retains its prior state after a manual reset, and in software standby mode.
Port G Register (PORTG)
Bit
:
7
6
5
4
—
—
—
PG4
Initial value : Undefined Undefined Undefined —*
R/W
:
—
—
—
R
Note: * Determined by state of pins PG4 to PG0.
3
PG3
—*
R
2
PG2
—*
R
1
PG1
—*
R
0
PG0
—*
R
PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port G pins (PG₄ to PG₀) must always be performed on PGDR.
Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified.
If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G
read is performed while PGDDR bits are cleared to 0, the pin states are read.
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