HD6432351 Datasheet, PDF (953/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

H8S/2351
Reset
R
Q
D
PAnPCR
C
WPCRA
RPCRA
*1
PA_n
*2
Mode 1/2/3/6/7
Mode 4/5
Reset
R
Q
D
PAnDDR
C
WDDRA
Reset
R
Q
D
PAnDR
C
WDRA
Reset
R
Q
D
PAnODR
C
WODRA
RODRA
RDRA
Legend
WDDRA : Write to PADDR
WDRA : Write to PADR
WODRA : Write to PAODR
WPCRA : Write to PAPCR
RDRA : Read PADR
RPORA : Read port A
RODRA : Read PAODR
RPCRA : Read PAPCR
n = 5 to 7
RPORA
Notes: 1. Output enable signal
2. Open drain control signal
Interrupt
controller
IRQ interrupt
input
Figure C-7 (c-1) H8S/2351 Port A Block Diagram (Pins PA₅ to PA₇)
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