HD6432351 Datasheet, PDF (67/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 2-3 Instructions Classified by Function (cont)
Type
Bit-
manipulation
instructions
Instruction
BXOR
Size*
B
BIXOR
B
BLD
B
BILD
B
BST
B
BIST
B
Note: * Size refers to the operand size.
B: Byte
Function
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a
general register or memory operand and stores the
result in the carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a
specified bit in a general register or memory operand
and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory
operand to the carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general
register or memory operand to the carry flag.
The bit number is specified by 3-bit immediate data.
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a
general register or memory operand.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a
specified bit in a general register or memory operand.
The bit number is specified by 3-bit immediate data.
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