HD6432351 Datasheet, PDF (325/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

8.3.9 Operation Timing
Figures 8-10 to 8-12 show an example of DTC operation timing.
ø
DTC activation
request
DTC
request
Address
Vector read
Data transfer
Read Write
Transfer
information read
Transfer
information write
Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
ø
DTC activation
request
DTC request
Address
Vector read
Data transfer
Read Write Read Write
Transfer
information read
Transfer
information write
Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
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