HD6432351 Datasheet, PDF (486/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TCLKA
TCLKB
Edge
detection
circuit
Channel 1
TCNT1
TGR1A
(speed period capture)
TGR1B
(position period capture)
TCNT0
+
TGR0A (speed control period)
–
TGR0C
+
(position control period)
–
TGR0B (pulse width capture)
TGR0D (buffer operation)
Channel 0
Figure 10-33 Phase Counting Mode Application Example
466