HD6432351 Datasheet, PDF (686/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 20-1 Operating Modes
Operating Transition Clearing
Mode
Condition Condition Oscillator
CPU
Registers
Modules
Registers I/O Ports
High speed Control
mode
register
Functions High Functions High Functions High speed
speed
speed
Medium- Control
speed mode register
Functions
Medium Functions
speed
High/ Functions
medium
speed *¹
High speed
Sleep mode Instruction Interrupt
Functions Halted Retained High Functions High speed
speed
Module stop Control
mode
register
Functions
High/ Functions
medium
speed
Halted Retained/
reset *²
Retained
Software
standby
mode
Instruction External
interrupt
Halted
Halted Retained Halted Retained/ Retained
reset *²
Hardware Pin
standby
mode
Halted
Halted Undefined Halted Reset
High
impedance
Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting
modules on the high-speed clock.
2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their
state.
20.1.1 Register Configuration
Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 20-2
summarizes these registers.
Table 20-2 Power-Down Mode Registers
Name
Abbreviation R/W
Standby control register
SBYCR
R/W
System clock control register
SCKCR
R/W
Module stop control register H MSTPCRH
R/W
Module stop control register L MSTPCRL
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'08
H'00
H'3F
H'FF
Address*
H'FF38
H'FF3A
H'FF3C
H'FF3D
666