HD6432351 Datasheet, PDF (576/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

13.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
MSTPCRL
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
R/W
: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
When the corresponding bit of bits MSTP6 and MSTP5 is set to 1, SCI operation stops at the end
of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written
to in module stop mode. For details, see section 20.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 6—Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode.
Bit 6
MSTP6
0
1
Description
SCI channel 1 module stop mode cleared
SCI channel 1 module stop mode set
(Initial value)
Bit 5—Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode.
Bit 5
MSTP5
0
1
Description
SCI channel 0 module stop mode cleared
SCI channel 0 module stop mode set
(Initial value)
556