HD6432351 Datasheet, PDF (314/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Table 8-2 outlines the functions of the DTC.
Table 8-2 DTC Functions
Address Registers
Transfer Mode
Transfer Transfer
Activation Source Source Destination
• Normal mode
• IRQ
24 bits 24 bits
 One transfer request transfers one byte or one
word
 Memory addresses are incremented or
decremented by 1 or 2
 Up to 65,536 transfers possible
• Repeat mode
 One transfer request transfers one byte or one
word
• TPU TGI
• SCI TXI or RXI
• A/D converter
ADI
• DMAC DEND
• Software
 Memory addresses are incremented or
decremented by 1 or 2
 After the specified number of transfers (1 to 256),
the initial state resumes and operation continues
• Block transfer mode
 One transfer request transfers a block of the
specified size
 Block size is from 1 to 256 bytes or words
 Up to 65,536 transfers possible
 A block area can be designated at either the
source or destination
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