HD6432351 Datasheet, PDF (264/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 7-11 illustrates operation in normal mode.
Address TA
Transfer
Address TB
Address BA
Legend
Address TA = LA
Address TB = LB
Address BA = LA + SAIDE • (–1)^SAID • (2^DTSZ • (N–1))
Address BB = LB + DAIDE • (–1)^DAID • (2^DTSZ • (N–1))
Where : LA = Value set in MARA
LB = Value set in MARB
N = Value set in ETCRA
Address BB
Figure 7-11 Operation in Normal Mode
Transfer requests (activation sources) are external requests and auto-requests.
With auto-request, the DMAC is only activated by register setting, and the specified number of
transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be
selected. In cycle steal mode, the bus is released to another bus master each time a transfer is
performed. In burst mode, the bus is held continuously until transfer ends.
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