HD6432351 Datasheet, PDF (676/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

18.2 Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can
be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to
the lower 8 bits. Word data must start at an even address.
The on-chip ROM is enabled and disabled by setting the mode pins (MD₂, MD₁, and MD₀). These
settings are shown in table 18-1.
In normal mode, a maximum of 56 kbytes of ROM can be used.
Table 18-1 Operating Modes and ROM Area
Operating Mode
Mode 1 Normal expanded mode with
on-chip ROM disabled
Mode 2 Normal expanded mode with
on-chip ROM enabled
Mode 3 Normal single-chip mode
Mode 4 Advanced expanded mode with
on-chip ROM disabled
Mode 5 Advanced expanded mode with
on-chip ROM disabled
Mode 6 Advanced expanded mode with
on-chip ROM enabled
Mode 7 Advanced single-chip mode
MD₂
0
Mode Pin
MD₁
0
MD₀
1
1
0
1
1
0
0
1
1
0
1
On-Chip ROM
Disabled
Enabled (56 kbytes)
Disabled
Enabled
656