HD6432351 Datasheet, PDF (546/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

ø
TCNT
Overflow signal
(internal signal)
H'FF
H'00
ø1
ø1
OVF
ø1
Figure 12-6 Timing of Setting of OVF
12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF)
The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time,
the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an
internal reset signal is generated for the entire H8S/2350 Series chip. Figure 12-7 shows the timing
in this case.
ø
TCNT
Overflow signal
(internal signal)
WOVF
WDTOVF signal
Internal reset
signal
H'FF
H'00
132 states
518 states
Figure 12-7 Timing of Setting of WOVF
526