HD6432351 Datasheet, PDF (470/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 10-17.
Input capture
signal
Buffer register
Timer general
register
TCNT
Figure 10-17 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
Set buffer operation
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2] Designate TGR for buffer operation with bits
[1]
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 to start the count
[2]
operation.
Start count
[3]
<Buffer operation>
Figure 10-18 Example of Buffer Operation Setting Procedure
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