HD6432351 Datasheet, PDF (883/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PADR—Port A Data Register
H'FF69
Port A
Bit
:
Initial value :
Read/Write :
7
PA7DR
0
R/W
6
PA6DR
0
R/W
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
Stores output data for port A pins (PA₇ to PA₀)
PBDR—Port B Data Register
H'FF6A
Port B
[H8S/2351 Only]
Bit
:
Initial value :
Read/Write :
7
PB7DR
0
R/W
6
5
PB6DR PB5DR
0
0
R/W R/W
4
3
PB4DR PB3DR
0
0
R/W R/W
2
PB2DR
0
R/W
1
0
PB1DR PB0DR
0
0
R/W R/W
Stores output data for port B pins (PB₇ to PB₀)
PCDR—Port C Data Register
H'FF6B
Port C
[H8S/2351 Only]
Bit
:
Initial value :
Read/Write :
7
PC7DR
0
R/W
6
PC6DR
0
R/W
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
Stores output data for port C pins (PC₇ to PC₀)
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