HD6432351 Datasheet, PDF (648/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Group
Selection
CH2
0
1
Channel Selection
CH1
CH0
0
0
1
1
0
1
0
0
1
1
0
1
Single Mode
AN0 (Initial value)
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Description
Scan Mode
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
15.2.3 A/D Control Register (ADCR)
Bit
:
7
6
5
4
3
2
1
0
TRGS1 TRGS0 —
—
—
—
—
—
Initial value :
0
0
1
1
1
1
1
1
R/W
: R/W
R/W
—
—
—
—
—
—
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of
the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion
is stopped (ADST = 0).
Bit 7
TRGS1
0
1
Bit 6
TRGS0
0
1
0
1
Description
A/D conversion start by software is enabled
(Initial value)
A/D conversion start by TPU conversion start trigger is enabled
—
A/D conversion start by external trigger pin (ADTRG) is enabled
Bits 5 to 0—Reserved: These bits are reserved; they are always read as 1 and cannot be
modified.
628