HD6432351 Datasheet, PDF (18/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

16.1.1 Features ................................................................................................................. 643
16.1.2 Block Diagram...................................................................................................... 644
16.1.3 Pin Configuration.................................................................................................. 645
16.1.4 Register Configuration.......................................................................................... 645
16.2 Register Descriptions ......................................................................................................... 646
16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 646
16.2.2 D/A Control Register (DACR) ............................................................................. 646
16.2.3 Module Stop Control Register (MSTPCR)........................................................... 648
16.3 Operation............................................................................................................................ 649
Section 17 RAM.................................................................................................................... 651
17.1 Overview............................................................................................................................ 651
17.1.1 Block Diagram...................................................................................................... 651
17.1.2 Register Configuration.......................................................................................... 652
17.2 Register Descriptions ......................................................................................................... 652
17.2.1 System Control Register (SYSCR)....................................................................... 652
17.3 Operation............................................................................................................................ 653
17.4 Usage Note ......................................................................................................................... 653
Section 18 ROM (H8S/2351 Only)................................................................................. 655
18.1 Overview............................................................................................................................ 655
18.1.1 Block Diagram...................................................................................................... 655
18.2 Operation............................................................................................................................ 656
Section 19 Clock Pulse Generator ................................................................................... 657
19.1 Overview............................................................................................................................ 657
19.1.1 Block Diagram...................................................................................................... 657
19.1.2 Register Configuration.......................................................................................... 658
19.2 Register Descriptions ......................................................................................................... 659
19.2.1 System Clock Control Register (SCKCR)............................................................ 659
19.3 Oscillator............................................................................................................................ 660
19.3.1 Connecting a Crystal Resonator............................................................................ 660
19.3.2 External Clock Input ............................................................................................. 662
19.4 Duty Adjustment Circuit.................................................................................................... 664
19.5 Medium-Speed Clock Divider ........................................................................................... 664
19.6 Bus Master Clock Selection Circuit................................................................................... 664
Section 20 Power-Down Modes ...................................................................................... 665
20.1 Overview............................................................................................................................ 665
20.1.1 Register Configuration.......................................................................................... 666
20.2 Register Descriptions ......................................................................................................... 667
20.2.1 Standby Control Register (SBYCR) ..................................................................... 667
20.2.2 System Clock Control Register (SCKCR)............................................................ 668
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