HD6432351 Datasheet, PDF (688/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 3—Output Port Enable (OPE): Specifies whether the output of the address bus and bus
control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance
state in software standby mode.
Bit 3
OPE
0
1
Description
In software standby mode, address bus and bus control signals are high-impedance
In software standby mode, address bus and bus control signals retain output state
(Initial value)
Bits 2 and 1—Reserved: Read-only bits, always read as 0.
Bit 0—Reserved: This bit can be read or written to, but only 0 should be written.
20.2.2 System Clock Control Register (SCKCR)
Bit
:
7
6
5
4
3
2
1
0
PSTOP —
—
—
—
SCK2 SCK1 SCK0
Initial value :
0
0
0
0
0
0
0
0
R/W
: R/W
R/W
—
—
—
R/W
R/W
R/W
SCKCR is an 8-bit readable/writable register that performs ø clock output control and medium-
speed mode control.
SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—ø Clock Output Disable (PSTOP): Controls ø output.
Bit 7
PSTOP
0
1
Normal
Operating Mode
ø output (initial value)
Fixed high
Description
Sleep Mode
Software
Standby Mode
ø output
Fixed high
Fixed high
Fixed high
Hardware
Standby Mode
High impedance
High impedance
Bits 6—Reserved: This bit can be read or written to, but only 0 should be written.
Bits 5 to 3—Reserved: Read-only bits, always read as 0.
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