HD6432351 Datasheet, PDF (191/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5.11 Refresh Control
The H8S/2350 Series is provided with a DRAM refresh control function. Either of two refreshing
methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing.
(1) CAS-before-RAS (CBR) Refreshing
To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in
DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control
is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing
is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in
RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM
used.
When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings
should therefore be completed before setting bits CKS2 to CKS0.
Do not clear the CMF flag when refresh control is being performed (RFSHE = 1).
RTCNT operation is shown in figure 6-23, compare match timing in figure 6-24, and CBR refresh
timings in figure 6-25.
RTCOR
RTCNT
H'00
Refresh request
Figure 6-23 RTCNT Operation
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