HD6432351 Datasheet, PDF (621/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

SCMR
SMIF
0
1
1
1
SMR
SCR Setting
C/A, GM CKE1
CKE0
See the SCI
0
0
0
0
0
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
SCK Pin Function
Operates as port I/O pin
Outputs clock as SCK output pin
Operates as SCK output pin, with output fixed
low
Outputs clock as SCK output pin
Operates as SCK output pin, with output fixed
high
Outputs clock as SCK output pin
14.3 Operation
14.3.1 Overview
The main functions of the Smart Card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If the error signal is sampled during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no clocked synchronous
communication function.
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