HD6432351 Datasheet, PDF (951/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

H8S/2351
*1
PA₄
*2
Mode 1/2/3/6/7
Mode 4/5
Reset
R
Q
D
PA4PCR
C
WPCRA
RPCRA
Mode
4/5*³ Reset
SR
Q
D
PA4DDR
C
WDDRA
Reset
R
Q
D
PA4DR
C
WDRA
Reset
R
Q
D
PA4ODR
C
WODRA
RODRA
RDRA
Legend
WDDRA : Write to PADDR
WDRA : Write to PADR
WODRA : Write to PAODR
WPCRA : Write to PAPCR
RDRA : Read PADR
RPORA : Read port A
RODRA : Read PAODR
RPCRA : Read PAPCR
RPORA
Notes: 1. Output enable signal
2. Open drain control signal
3. Set priority
Interrupt
controller
IRQ interrupt
input
Figure C-7 (b-1) H8S/2351 Port A Block Diagram (Pin PA₄)
931