HD6432351 Datasheet, PDF (154/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2.6 Memory Control Register (MCR)
Bit
:
Initial value :
R/W
:
7
TPC
0
R/W
6
5
4
3
2
1
0
BE RCDM CW2 MXC1 MXC0 RLW1 RLW0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number
of precharge cycles, access mode, address multiplexing shift size, and the number of wait states
inserted during refreshing, when areas 2 to 5 are designated as DRAM interface.
MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T_P) is to be
used when areas 2 to 5 designated as DRAM space are accessed.
Bit 7
TPC
0
1
Description
1-state precharge cycle is inserted
2-state precharge cycle is inserted
(Initial value)
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5
designated as DRAM space. DRAM space burst access is performed in fast page mode.
Bit 6
BE
0
1
Description
Burst disabled (always full access)
For DRAM space access, access in fast page mode
(Initial value)
134