HD6432351 Datasheet, PDF (189/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

(2) RAS Down Mode and RAS Up Mode
Even when burst operation is selected, it may happen that access to DRAM space is not
continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low
during the access to the other space, burst operation can be resumed when the same row address in
DRAM space is accessed again.
• RAS down mode
To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is
interrupted and another space is accessed, the RAS signal is held low during the access to the
other space, and burst access is performed if the row address of the next DRAM space access
is the same as the row address of the previous DRAM space access. Figure 6-21 shows an
example of the timing in RAS down mode.
Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down
mode.
DRAM access
External space
access
DRAM access
T_p
T_r
T_c1
T_c2
T₁
T₂
T_c1
T_c2
ø
A₂₃ to A₀
CSn (RAS)
CAS, LCAS
D₁₅ to D₀
Note: n = 2 to 5
Figure 6-21 Example of Operation Timing in RAS Down Mode
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