HD6432351 Datasheet, PDF(303/989 Page) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HD6432351 Datasheet, PDF (303/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

◁

Section 8 Data Transfer Controller

8.1 Overview

The H8S/2350 Series includes a data transfer controller (DTC). The DTC can be activated by an

interrupt or software, to transfer data.

8.1.1 Features

The features of the DTC are:

â¢ Transfer possible over any number of channels

ï£§ Transfer information is stored in memory

ï£§ One activation source can trigger a number of data transfers (chain transfer)

â¢ Wide range of transfer modes

ï£§ Normal, repeat, and block transfer modes available

ï£§ Incrementing, decrementing, and fixing of source and destination addresses can be selected

â¢ Direct specification of 16-Mbyte address space possible

ï£§ 24-bit transfer source and destination addresses can be specified

â¢ Transfer can be set in byte or word units

â¢ A CPU interrupt can be requested for the interrupt that activated the DTC

ï£§ An interrupt request can be issued to the CPU after one data transfer ends

ï£§ An interrupt request can be issued to the CPU after the specified data transfers have

completely ended

â¢ Activation by software is possible

â¢ Module stop mode can be set

ï£§ The initial setting enables DTC registers to be accessed. DTC operation is halted by setting

module stop mode.

283

▷