HD6432351 Datasheet, PDF (136/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

5.6 DTC and DMAC Activation by Interrupt
5.6.1 Overview
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used with to activate the DTC or DMAC, see section 8,
Data Transfer Controller, and section 7, DMA Controller.
5.6.2 Block Diagram
Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller.
DMAC
Interrupt
request
IRQ
interrupt
Interrupt source
On-chip
clear signal
supporting
module
Selection
circuit
Select
signal
Clear signal
DTCER
DTVECR
SWDTE
clear signal
Control logic
Interrupt controller
Determination of
priority
DTC activation
request vector
number
Clear signal
DTC
CPU interrupt
request vector
number
I, I2 to I0
CPU
Figure 5-9 Interrupt Control for DTC and DMAC
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